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? freescale semiconductor, inc., 20 05, 2006, 2007. all rights reserved. freescale semiconductor technical data freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. document number: mc1321x rev. 1.2 05/2007 mc1321x package information case 1664-01 71-pin lga [9x9 mm] ordering information device device marking package mc13211 1 1 see table 1 for more details. 13211 lga mc13212 1 13212 lga mc13213 1 13213 lga 1 introduction the mc1321x family is frees cale?s second-generation zigbee platform which in corporates a low power 2.4 ghz radio frequency tran sceiver and an 8-bit microcontroller into a single 9x9x1 mm 71-pin lga package. the mc1321x solution can be used for wireless applications from simple proprietary point-to-point connectivity to a complete zigbee mesh network. the combination of the radio and a microcont roller in a small footprint package allows for a cost-effective solution. the mc1321x contains an rf transceiver which is an 802.15.4 standard compliant radio that operates in the 2.4 ghz ism frequency band. the transceiver includes a low noise amplifier, 1mw nominal output power, pa with internal voltage cont rolled oscillator (vco), integrated transmit/recei ve switch, on-board power supply regulation, and full spread-spectrum encoding and decoding. the mc1321x also contains a microcontroller based on the hcs08 family of micr ocontroller units (mcu), specifically the hcs08 versi on a, and can provide up to 60kb of flash memory and 4kb of ram. the onboard mc13211/212/213 zigbee ? - compliant platform - 2.4 ghz low power transceiver for the ieee ? 802.15.4 standard plus microcontroller contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 mc1321x pin assignment and connections 8 3 mc1321x serial peripheral interface (spi) . 14 4 802.15.4 standard modem . . . . . . . . . . . . . . 16 5 mcu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 system electrical specification . . . . . . . . . 45 7 application considerations . . . . . . . . . . . . . 62 8 mechanical diagrams . . . . . . . . . . . . . . . . . . 67
mc13211/212/213 technical data, rev. 1.2 2 freescale semiconductor mcu allows the communications stack and also the ap plication to reside on th e same system-in-package (sip). the mc1321x family is organized as follows: ? the mc13211 has 16kb of flash and 1kb of ra m and is an ideal solution for low cost, proprietary applications that require wireless point-to-point or star network connectivity. the mc13211 combined with the freescale simple mac (smac) provides the foundation for proprietary applications by supplying the necessary source code and application examples to get users started on implementi ng wireless connectivity. ? the mc13212 contains 32k of flas h and 2kb of ram and is intende d for use with the freescale fully compliant 802.15.4 mac. custom networks based on the 802.15.4 standard mac can be implemented to fit user needs. the 802.15.4 sta ndard supports star, mesh and cluster tree topologies as well as beaconed networks. ? the mc13213 contains 60k of flash and 4kb of ram and is also intended for use with the freescale fully compliant 802.15.4 mac where larger memory is require d. in addition, this device can support zigbee 2006 applications that use freescale?s beestack. applications include, but are not limited to, the following: ? residential and commercial automation ? lighting control ? security ? access control ? heating, ventilation, air-conditioning (hvac) ? automated meter reading (amr) ? industrial control ? asset tracking and monitoring ? homeland security ? process management ? environmental mon itoring and control ? hvac ? automated meter reading ? health care ? patient monitoring ? fitness monitoring ? consumer ? human interface devices (keyboard, mice, etc.) ? remote control ? wireless toys
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 3 1.1 ordering information table 1 provides additional details about the mc1321x family. 1.2 general platform features ? 802.15.4 standard compliant on-chip transceiver/modem ? 2.4ghz ? 16 selectable channels ? programmable output power ? multiple power saving modes ? 2v to 3.4v operating voltage wi th on-chip voltage regulators ? -40c to +85c temperature range ? low external component count ? supports single 16 mhz crystal clock sour ce operation or dua l crystal operation ? support for smac, 802.15.4 standard, and zigbee software ? 9mm x 9mm x 1mm 71-pin lga table 1. orderable parts details device operating temp range (ta.) package memory options description mc13211 -40 to 85 c lga 1kb ram, 16kb flash intended for proprietary applications and freescale simple mac (smac) mc13211r2 -40 to 85 c lga tape and reel 1kb ram, 16kb flash intended for proprietary applications and freescale simple mac (smac) mc13212 -40 to 85 c lga 2kb ram, 32kb flash intended for 802.15.4 standard compliant applications and freescale 802.15.4 mac MC13212R2 -40 to 85 c lga tape and reel 2kb ram, 32kb flash intended for 802.15.4 standard compliant applications and freescale 802.15.4 mac mc13213 -40 to 85 c lga 4kb ram, 60kb flash intended for 802.15.4 standard compliant applications and freescale 802.15.4 mac. in addition, this device can support zigbee 2006 applications that use freescale?s beestack. mc13213r2 -40 to 85 c lga tape and reel 4kb ram, 60kb flash intended for 802.15.4 standard compliant applications and freescale 802.15.4 mac. in addition, this device can support zigbee 2006 applications that use freescale?s beestack.
mc13211/212/213 technical data, rev. 1.2 4 freescale semiconductor 1.3 microcontroller features ? low voltage mcu with 40 mhz low power hcs08 cpu core ? up to 60k flash memory with block protection and security and 4k ram ? mc13211: 16kb flash, 1kb ram ? mc13212: 32kb flash, 2kb ram ? mc13213: 60kb flash, 4kb ram ? low power modes (wait plus stop2 and stop3 modes) ? dedicated serial peripheral interface (s pi) connected internally to 802.15.4 modem ? one 4-channel and one 1-cha nnel 16-bit timer/pulse width modulator (tpm) module with selectable input capture, output capture, and pwm capability. ? 8-bit port keyboard interrupt (kbi) ? 8-channel 8-10-bit adc ? two independent serial co mmunication interfaces (sci) ? multiple clock source options ? internal clock generator (icg) with 243 khz os cillator that has +/-0.2% trimming resolution and +/-0.5% deviation across voltage. ? startup oscillator of approximately 8 mhz ? external crystal or resonator ? external source from modem clock for very hi gh accuracy source or system low-cost option ? inter-integrated ci rcuit (iic) interface. ? in-circuit debug and flash programming availa ble via on-chip background debug module (bdm) ? two comparator and 9 trigger modes ? eight deep fifo for storing change -of-flow addresses and event-only data ? tag and force breakpoints ? in-circuit debugging wi th single breakpoint ? system protection features ? programmable low volta ge interrupt (lvi) ? optional watchdog timer (cop) ? illegal opcode detection ? up to 32 mcu gpio with programmable pullups
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 5 1.4 rf modem features ? fully compliant 802.15.4 standard transceiver supports 250 kbps o-qpsk data in 5.0 mhz channels and full spread-spectrum encode and decode ? operates on one of 16 selectable channels in the 2.4 ghz ism band ? -1 dbm to 0 dbm nominal ou tput power, programmable from -27 dbm to +3 dbm typical ? receive sensitivity of <-92 dbm (typical) at 1% per, 20-byte packet, much better than the 802.15.4 standard of -85 dbm ? integrated transm it/receive switch ? dual pa ouput pairs which can be programmed for full differential single-port or dual-port operation that supports an external lna and/or pa. ? three low power modes fo r increased battery life ? programmable frequency clock output for use by mcu ? onboard trim capability for 16 mhz crystal refere nce oscillator eliminates need for external variable capacitors and allows for automated production fre quency calibration ? four internal timer comparators availa ble to supplement mcu timer resources ? supports both packet data mode and streaming data mode ? seven gpio to supplement mcu gpio 1.5 software features freescale provides a wide range of software functionality to comp lement the mc1321x hardware. there are three levels of application solutions: 1. simple proprietary wireless connectivity. 2. user networks built on the 802.15.4 mac standard. 3. zigbee 2006 compliant, freescale beestack. 1.5.1 simple mac (smac) ? small memory footprint (about 3 kbytes typical) ? supports point-to-point and st ar network configurations ? proprietary networks ? source code and applicat ion examples provided 1.5.2 802.15.4 standard-compliant mac ? supports star, mesh and cluster tree topologies ? supports beaconed networks ? supports gts for low latency ? multiple power saving mode s (idle doze, hibernate)
mc13211/212/213 technical data, rev. 1.2 6 freescale semiconductor 1.5.3 zigbee 2006-compliant. freescale beestack ? supports zigbee 2006 specification ? supports star, mesh and tree networks ? advanced encryption standa rd (aes) 128-bit security 1.6 system block diagram figure 1 shows a simplified block diagram of the mc1321x solution. figure 1. mc1321x system level block diagram digital transceiver transmit/receiv e sw itch analog receiv er analog transmitter frequency generator buffer ram irq arbiter ram arbiter power management voltage regulators hcs08 cpu 16-60 kb flash memory 1-4 kb ram low voltage detect keyboard interrupt internal clock generator up to 32 gpio cop 1 channel & 4 channel 16-bit timers i 2 c 2x sci 8 channel 10 bit adc background debug module rfic timers di gi tal control logic dedi c ated spi 802.15.4 modem hcs08 mcu rin_p(pao_p) rin_m(pao_m) pao_p pao_m
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 7 1.7 system clock configuration the mc321x device allows for a wide ar ray of system clock configurations: ? pins are provided for a se parate external clock s ource for the cpu. the ex ternal clock source can by derived from a crystal oscillator or from an external clock source ? pins are provided for a 16 mhz crystal for the modem clock source (required) ? the modem crystal oscillator frequency can be trimmed through pr ogramming to maintain the tight tolerances required by the 802.15.4 standard ? the modem provides a clko pr ogrammable frequency clock output that can be used as an external source to the cpu. as a result, a single crystal system cl ock solution is possible ? out of reset, the mcu uses an internally generated clock (approxi mately 8-mhz) for start-up. this allows recovery from stop or reset without a long crystal start-up delay ? the mcu contains an internal cl ock generator (which can be trimme d) that can be used to run the mcu for low power operation. this intern al reference is approximately 243 khz figure 2. mc1321x single crystal system clock structure 802.15.4 modem hcs08 mcu xtal1 xtal2 clko extal xtal mc1321x 27 28 10 98 16mhz
mc13211/212/213 technical data, rev. 1.2 8 freescale semiconductor 2 mc1321x pin assignment and connections figure 3 shows the mc1321x pinout. figure 3. mc1321x pinout (top view) 32 pta0/kbi1p0 vrefl ptb7/ad1p7 ptb6/ad1p6 ptb5/ad1p5 ptb4/ad1p4 ptb3/ad1p3 ptb1/ad1p1 ptb0/ad1p0 pta1/kbi1p1 vrefh ptd6/tpm2ch3 ptb2/ad1p2 pta4/kbi1p4 pta5/kbi1p5 pta7/kbi1p7 vddad ptg1/xtal ptg2/extal ptc0/txd2 ptc1/rxd2 ptc4 ptc2/s da1 ptc3/s cl1 pta3/kbi1p3 ptc5 ptc6 ptc7 pte0/txd1 pte1/rxd1 vddd vddint gpio5 gpio6 gpio7 xtal1 xtal2 vddlo2 vddlo1 vddvco vbatt ptd2/tpm1ch2 clko vdd gpio1 gpio2 gpio3 gpio4 sm pao_m pao_p rfin_m rfin_p vdda nc ct_bias mc1321x 1 16 17 33 48 49 64 pta6/kbi1p6 2 3 4 5 6 7 8 9 10 11 12 13 14 15 47 46 45 44 43 42 41 40 39 38 37 36 35 34 18 19 20 21 22 23 24 25 26 27 28 29 30 31 63 62 61 60 59 58 57 56 55 54 53 52 51 50 65 66 67 68 69 71 70 flag opening ptd4/tpm2ch1 pta2/kbi1p2 ptd5/tpm2ch2 ptd7/tpm2ch4 tes t tes t res et attn ptg0/bkgd/ms flag opening
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 9 2.1 pin definitions table 2 details the mc1321x pinout and functionality. table 2. pin function description pin # pin name type description functionality 1 pta3/kbi1p3 digital input/output mcu port a bit 3 / keyboard input bit 3 2 pta4/kbi1p4 digital input/output mcu port a bit 4 / keyboard input bit 4 3 pta5/kbi1p5 digital input/output mcu port a bit 5 / keyboard input bit 5 4 pta6/kbi1p6 digital input/output mcu port a bit 6 / keyboard input bit 6 5 pta7/kbi1p7 digital input/output mcu port a bit 7 / keyboard input bit 7 6 vddad power input mcu power supply to atd decouple to ground. 7 ptg0/bkgnd/ms digital input/output mcu port g bit 0 / background / mode select ptg0 is output only. pin is i/o when used as bdm function. 8 ptg1/xtal digital input/output/ output mcu port g bit 1 / crystal oscillator output full i/o when not used as clock source. 9 ptg2/extal digital input/output/ input mcu port g bit 2 / crystal oscillator input full i/o when not used as clock source. 10 clko digital output modem clock output programmable frequencies of: 16 mhz, 8 mhz, 4 mhz, 2 mhz, 1 mhz, 62.5 khz, 32.786+ khz (default), and 16.393+ khz. 11 reset digital input/output mcu reset. active low 12 ptc0/txd2 digital input/output mcu port c bit 0 / sci2 tx data out 13 ptc1/rxd2 digital input/output mcu port c bit 1/ sci2 rx data in 14 ptc2/sda1 digital input/output mcu port c bit 1/ iic bus data 15 ptc3/scl1 digital input/output mcu port c bit 1/ iic bus clock 16 ptc4 digital input/output mcu port c bit 4 17 ptc5 digital input/output mcu port c bit 5
mc13211/212/213 technical data, rev. 1.2 10 freescale semiconductor 18 ptc6 digital input/output mcu port c bit 6 19 ptc7 digital input/output mcu port c bit 7 20 pte0/txd1 digital input/output mcu port e bit 0 / sci1 tx data out 21 pte1/rxd1 digital input/output mcu port e bit 1/ sci1 rx data in 22 vddd power output modem regulated output supply voltage decouple to ground. 23 vddint power input modem digital interface supply 2.0 to 3.4 v. decouple to ground. connect to battery. 24 gpio5 1 digital input/output general purpose input/output 5. see footnote 1 25 gpio6 digital input/output modem general purpose input/output 6 26 gpio7 digital input/output modem general purpose input/output 7 27 xtal1 input modem crystal reference oscillator input connect to 16 mhz crystal and load capacitor. 28 xtal2 input/output modem crystal reference oscillator output connect to 16 mhz crystal and load capacitor. do not load this pin by using it as a 16 mhz source. measure 16 mhz output at clko, programmed for 16 mhz. 29 vddlo2 power input modem lo2 vdd supply connect to vdda externally. 30 vddlo1 power input modem lo1 vdd supply connect to vdda externally. 31 vddvco power output modem vco regulated supply bypass decouple to ground. 32 vbatt power input modem voltage regulators? input decouple to ground. connect to battery. 33 vdda power output modem analog regulated supply output decouple to ground. connect to directly vddlo1 and vddlo2 externally and to pao_p and pao_m through a bias network. 34 ct_bias rf control output modem bias voltage/control signal for rf external components when used with internal t/r switch, provides ground reference for rx and vdda reference for tx. can also be used as a control signal with external lna, antenna switch, and/or pa. 35 rfin_m rf input (output) modem rf input/output negative when used with internal t/r switch, this is a bi-directional rf port for the internal lna and pa 36 rfin_p rf input (output) modem rf input/output positive when used with internal t/r switch, this is a bi-directional rf port for the internal lna and pa table 2. pin function description (continued) pin # pin name type description functionality
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 11 37 nc not used may be grounded or left open 38 pao_p rf output modem power amplifier rf output positive open drain. connect to vdda through a bias network when used with external balun. not used when internal t/r switch is used. 39 pao_m rf output modem power amplifier rf output negative open drain. connect to vdda through a bias network when used with external balun. not used when internal t/r switch is used. 40 sm input test mode pin must be grounded for normal operation 41 gpio4 1 digital input/ output general purpose input/output 4. see footnote 1 42 gpio3 digital input/output modem general purpose input/output 3 43 gpio2 test point mcu port e bit 6 / modem general purpose input/output 2 internally connected pins. when gpio_alt_en, register 9, bit 7 = 1, gpio2 functions as a ?crc valid? indicator. 44 gpio1 test point mcu port e bit 7 / modem general purpose input/output 1 internally connected pins. when gpio_alt_en, register 9, bit 7 = 1, gpio1 functions as an ?out of idle? indicator. 45 vdd power input mcu main power supply decouple to ground. 46 attn 2 digital input active low attention. transitions ic from either hibernate or doze modes to idle. see footnote 2 47 ptd2/tpm1ch2 digital input/output mcu port d bit 2 / tpm1 channel 2 48 ptd4/tpm2ch1 digital input/output mcu port d bit 4 / tpm2 channel 1 49 ptd5/tpm2ch2 digital input/output mcu port d bit 5 / tpm2 channel 2 50 ptd6/tpm2ch3 digital input/output mcu port d bit 6 / tpm2 channel 3 51 ptd7/tpm2ch4 digital input/output mcu port d bit 7 / tpm2 channel 4 52 ptb0/ad1p0 input/output mcu port b bit 0 / atd analogchannel 0 53 ptb1/ad1p1 input/output mcu port b bit 1 / atd analog channel 1 54 ptb2/ad1p2 input/output mcu port b bit 2 / atd analog channel 2 55 ptb3/ad1p3 input/output mcu port b bit 3 / atd analog channel 3 table 2. pin function description (continued) pin # pin name type description functionality
mc13211/212/213 technical data, rev. 1.2 12 freescale semiconductor 56 ptb4/ad1p4 input/output mcu port b bit 4 / atd analog channel 4 57 ptb5/ad1p5 input/output mcu port b bit 5 / atd analog channel 5 58 ptb6/ad1p6 input/output mcu port b bit 6 / atd analog channel 6 59 ptb7/ad1p7 input/output mcu port b bit 7 / atd analog channel 7 60 vrefh input mcu high reference voltage for atd 61 vrefl input mcu low reference voltage for atd 62 pta0/kbi1p0 digital input/output mcu port a bit 0 / keyboard input bit 0 63 pta1/kbi1p1 digital input/output mcu port a bit 1 / keyboard input bit 1 64 pta2/kbi1p2 digital input/output mcu port a bit 2 / keyboard input bit 2 65 test test point for factory test do not connect 66 test test point for factory test do not connect 67 test test point for factory test do not connect 68 test test point for factory test do not connect 69 test test point for factory test do not connect 70 test test point for factory test do not connect 71 test test point for factory test do not connect flag vss power input external package flag. common vss connect to ground. 1 the transceiver gpio pins default to inputs at reset. ther e are no programmable pullups on these pins. unused gpio pins should be tied to ground if left as inputs, or if left uncon nected, they should be programmed as outputs set to the low state. 2 during low power modes, input must remain driven by mcu. table 2. pin function description (continued) pin # pin name type description functionality
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 13 2.2 internal functional interconnects the mcu provides control for the 802.15.4 modem. the required interconnects between the devices are routed onboard the sip. in addition, the signals are br ought out to external pads primarily for use as test points. these signals can be useful when writing and debugging software. note to use the mcu and modem signals as described in table 3 , the mcu needs to be programmed appropria tely for the st ated function. table 3. internal functional interconnects pin # mcu signal modem signal description 43 pte6 gpio2 modem gpio2 output acts as ?crc valid? status indicator for stream data mode to mcu. 44 pte7 gpio1 modem gpio1 output acts as ?out of idle? status indicator for stream data mode to mcu. 46 ptd0 attn mcu port d bit 0 drives the attention (attn ) input of the modem to wake modem from hibernate or doze mode. pte5/spsck1 spiclk 1 1 during low power modes, input must remain driven by mcu. mcu spi master spi clock output dr ives modem spiclk slave clock input. pte4/mosi1 mosi 1 mcu spi master mosi output dr ives modem slave mosi input pte3/miso1 miso 2 2 by default miso is tri-stated when ce is negated. for low power operation, miso _hiz_en (bit 11, register 07) should be set to zero so that miso is driven low when ce is negated. modem spi slave miso output drives mcu master miso input pte2/ss1 ce 1 mcu spi master ss output drives modem slave ce input irq m_irq modem interrupt request m_irq output drives mcu irq input ptd1 rxtxen 1 mcu port d bit 1 drives the rxtxen input to the modem to enable tx or rx or cca operations. ptd3 m_rst mcu port d bit 3 drives the reset m_rst input to the modem.
mc13211/212/213 technical data, rev. 1.2 14 freescale semiconductor 3 mc1321x serial peripheral interface (spi) the mc1321x modem and cpu communicate primarily through the onboard spi command channel. figure 4 shows the sip internal interconnects with th e spi bus highlighted. the mcu has a single spi module that is dedicated to the m odem spi interface. the modem is a slave only and the mcu spi must be programmed and used as a master only. furthe r, the spi performance is limited by the modem constraints of 8 mhz spi clock fr equency, and use of the spi must be programmed to meet the modem spi protocol. 3.1 sip level spi pin connections the sip level spi pin connections are all internal to the device. figure 4 shows the sip interconnections with the spi bus highlighted. figure 4. mc1321x internal interconnects highlighting spi bus table 4. mc1321x internal spi connections mcu signal modem signal description pte5/spsck1 spiclk mcu spi master spi clock out put drives modem spiclk slave clock input. pte4/mosi1 mosi mcu spi master mosi output drives modem slave mosi input pte3/miso1 miso modem spi slave miso ou tput drives mcu master miso input pte2/ss1 ce mcu spi master ss output drives modem slave ce input m_rst ptd3 m_irq attn rxtxen gpio1/out_of_idle gpio2/crc_valid mosi miso spiclk irq ptd0 ptd1 pte7 pte6 pte4/mosi1 pte3/miso1 pte5/spsck1 ce pte2/ss1 modem mcu reset 47 44 43 11 mc1321x
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 15 3.2 spi features ? mcu bus master ? modem bus slave ? programmable spi clock rate ; maximum rate is 8 mhz ? double-buffered transmit and receive at mcu ? serial clock phase and polarity must meet modem requirements (mcu control bits ? slave select programmed to meet modem protocol 3.3 spi system block diagram figure 5 shows the spi system level diagram. figure 5. spi system block diagram figure 5 shows the spi modules of the mcu and mode m in the master-slave arrangement. the mcu (master) initiates all spi transfers. during a transfer, the master shifts data out (on the mosi pin) to the slave while simultaneously shifting data in (on the mi so pin) from the slave. although the spi interface supports simultaneous data exchange between master and slave, the m odem spi protocol only uses data exchange in one direction at a time. the spsck signal is a clock output from the master and an input to the slave. the slave device must be selected by a low level on the slave select input (ss1 pin). 7 6 5 4 3 2 1 0 spi shifter clock generator 7 6 5 4 3 2 1 0 spi shifter pte2/s s 1 spsck1 miso1 mos1 ce spiclk miso mosi mcu (master) modem (slave)
mc13211/212/213 technical data, rev. 1.2 16 freescale semiconductor 4 802.15.4 standard modem 4.1 block diagram figure 6. 802.15.4 standard modem block diagram phase shift modulator rst gpio1 gpio2 gpio3 gpio4 xtal2 xtal1 rfin_m (pao_m) pao_p pao_m mosi miso spiclk rxtxen ce attn gpio5 gpio6 gpio7 receive packet ram transmit packet ram 1 transmit ram arbiter receiv e ram arbiter pa vco crystal oscillator sy mbol generation fcs generation header generation mux sequence manager (control logic) vd d l o2 4 256 mhz 2.45 ghz lna 1st if mix er if = 65 mhz 2nd if mix er if = 1 mhz pma decimation filter matched filter baseband mixer dcd correlator symbol synch & det cca packet processor irq arbiter 24 bit ev ent timer irq 16 mhz agc analog regulator vbatt digital regulator l digital regulator h pow er-up control logic crystal regulator vco regulator vddint programmable prescaler clko 4 programmable timer comparators sy nthesizer vddd vddvco serial peripheral interface (spi) vdda vddlo1 transmit packet ram 2 t / r rfin_p (pao_p) ct_bias
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 17 4.2 data transfer modes the 802.15.4 modem has two data transfer modes: 1. packet mode ? data is buffered in on-chip ram 2. streaming mode ? data is processed word-by-word the freescale 802.15.4 mac softwa re only supports the streaming mode of data transfer. for proprietary applications, packet mode can be used to conserve mcu resources. 4.3 packet structure figure 7 shows the packet structure of the 802.15.4 mode m. payloads of up to 125 bytes are supported. the 802.15.4 modem adds a fo ur-byte preamble, a one-byte start of frame delimiter (sfd), and a one-byte frame length indicator (fl i) before the data. a frame check sequence (fcs) is calculated and appended to the end of the data. figure 7. 802.15.4 modem packet structure 4.4 receive path description in the receive signal path, the rf input is converted to low if in-phase and qu adrature (i & q) signals through two down-conversion stages. a clear channel assessment (cca ) can be performed based upon the baseband energy integrated over a specific time in terval. the digital back end performs differential chip detection (dcd), the correlator ?de-spreads? the direct sequence spread spectrum (dsss) offset qpsk (o-qpsk) signal, determines the sy mbols and packets, and detects the data. the preamble, sfd, and fli are parsed and used to detect the payload da ta and fcs (which are stored in ram in packet mode). a two-byte fcs is calculated on the received data and compared to the fcs value appended to the transmitted data, which genera tes a cyclical redundancy check (crc) result. a parameter of received ener gy during the reception called the link qu ality indicator is measured over a 64 s period after the packet preamble and stored in an spi register. if the 802.15.4 modem is in packet mode, the data is st ored in ram and processe d as an entire packet. the mcu is notified that an entire pack et has been received via an interrupt. if the 802.15.4 modem is in streaming mode, the mcu is notified by a re curring interrupt on a word-by-word basis. figure 8 shows cca reported power level versus input power. note th at cca reported power saturates at about -57 dbm input power which is we ll above 802.15.4 standa rd requirements. figure 9 shows energy detection/lqi reported le vel versus input power. preamble sfd fli payload data fcs 4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes
mc13211/212/213 technical data, rev. 1.2 18 freescale semiconductor note for both graphs, the required 802.15.4 standard accuracy and range limits are shown. a 3.5 dbm offset has been programmed into the cca reporting level to center the level ove r temperature in the graphs. figure 8. reported power level versus input power in clear channel assessment mode figure 9. reported power level versus input power for energy detect or link quality indicator -100 -90 -80 -70 -60 -50 -90 -80 -70 -60 -50 input pow er (dbm) reported power level (dbm) 802.15.4 accuracy and range requirements -85 -75 -65 -55 -45 -35 -25 -15 -85 -75 -65 -55 -45 -35 -25 -15 r epor t e d p ower l eve l (db m ) 802.15.4 accuracy and range requirements
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 19 4.5 transmit path description for the transmit path, the tx data that was previously written to the internal ram is retrieved (packet mode) or the tx data is clocked in via the spi (stream mode), form ed into packets per the 802.15.4 phy, spread, and then up-converted to the transmit frequency. if the 802.15.4 modem is in packet mode, data is processed as an entire packet. the da ta is first loaded into the tx buffer. the mcu then requests that the mode m transmit the data. the mcu is notified via an interrupt when the whole packet ha s successfully been transmitted. in streaming mode, the data is fed to the 802.15.4 m odem on a word-by-word basis with an interrupt serving as a notification that the 802.15.4 modem is ready for more data. this continues until the whole packet is transmitted. in both modes, a two-byte fcs is calculated in hardwa re from the payload data and appended to the packet. this done without intervention from the user. 4.6 functional description the following sections provide a detailed description of the mc 1321x functionality including the operating modes and the serial peripheral interface (spi). 4.6.1 802.15.4 modem operational modes the 802.15.4 modem has a number of operational modes that allow for low-current operation. transition from the off to idle mode occurs when m_rst is negated. once in idle, the spi is active and is used to control the ic. transition to hibernate and doze modes is enabled via the spi. these modes are summarized, along with the transition times, in table 5 . current drain in the various modes is listed in table 8 , dc electrical characteristics. table 5. 802.15.4 modem mode defi nitions and transition times mode definition transition time to or from idle off all ic functions off, leakage only. m_rs t asserted. digital outputs are tri-stated including irq 10 - 25 ms to idle hibernate crystal reference oscillator off. (spi not functional.) ic responds to attn . data is retained. 7 - 20 ms to idle doze crystal reference oscillator on but clko ou tput available only if register 7, bit 9 = 1 for frequencies of 1 mhz or less. (spi not functional.) responds to attn and can be programmed to enter idle mode through an internal timer comparator. (300 + 1/clko) s to idle idle crystal reference oscillator on with cl ko output available. spi active. receive crystal reference oscillator on. receiver on. 144 s from idle transmit crystal reference oscillator on. transmitter on. 144 s from idle
mc13211/212/213 technical data, rev. 1.2 20 freescale semiconductor 4.6.2 serial peripheral interface (spi) the mcu directs the 802.15.4 modem, checks its status, a nd reads/writes data to the device through the 4-wire spi port. the transceiver operates as a spi slave device only. a transaction between the host and the 802.15.4 modem occurs as multiple 8-bit bu rsts on the spi. the modem spi signals are: 1. chip enable (ce ) - a transaction on the spi port is framed by the active low ce input signal. a transaction is a minimum of 3 spi bursts a nd can extend to a greater number of bursts. 2. spi clock (spiclk) - the host drives the spiclk input to the 802.15.4 modem. data is clocked into the master or slave on the leading (rising) edge of the return-to-zero spiclk and data out changes state on the trailing (falling) edge of spiclk. note for the mcu, the spi clock format is the clock phase cont rol bit cpha = 0 and the clock polarity control bit cpol = 0. 3. master out/slave in (mosi) - incoming data from the host is presented on the mosi input. 4. master in/slave out (miso) - the 802.15.4 modem presents data to the master on the miso output. although the spi port is fully static, in ternal memory, timer and interrupt arbiters require an internal clock (clk core ), derived from the crystal refere nce oscillator, to communicate from the spi registers to internal registers and memory. 4.6.2.1 spi burst operation the spi port of the mcu transf ers data in bursts of 8 bi ts with most significant bi t (msb) first. the master (mcu) can send a byte to the slave (transceiver) on the mosi line and the slave can send a byte to the master on the miso line. although an 802.15.4 modem tran saction is three or mo re spi bursts long, the timing of a single spi burst is shown in figure 10 . the maximum spi clock rate is 8 mhz from the mcu because the modem is limited by this number. figure 10. spi single burst timing diagram 1 2345 678 ce spiclk spi burst valid valid miso mosi
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 21 4.6.2.2 spi transaction operation although the spi port of the mcu transfers data in bursts of 8 bits, the 802.15.4 modem requires that a complete spi transaction be framed by ce , and there will be three (3) or more bursts per transaction. the assertion of ce to low signals the start of a tr ansaction. the first spi burst is a write of an 8-bit header to the transceiver (mosi is valid) th at defines a 6-bit address of the internal resource being accessed and identifies the access as bei ng a read or write operation. in this context, a write is data written to the 802.15.4 modem and a read is data wr itten to the spi master. th e following spi bursts will be either the write data (mosi is valid) to the transceiver or read data from the transceiver (miso is valid). although the spi bus is capable of sending data si multaneously between master and slave, the 802.15.4 modem never uses this mode. the num ber of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. after the final spi burst, ce is negated to high to signal the end of the transaction. an example spi read transaction wi th a 2-byte payload is shown in figure 11 . figure 11. spi read transaction diagram ce spiclk miso mosi valid valid valid clock burst header read data
mc13211/212/213 technical data, rev. 1.2 22 freescale semiconductor 4.7 modem crystal oscillator the modem crystal oscillator uses the following external pins as shown in figure 12 . 1. xtal1 - reference oscillator input. 2. xtal2 - reference oscillator output . note that this pin should not be loaded as a reference source or to measure frequency; instead us e clko to measure or supply 16 mhz. figure 12. modem crystal oscillator the 802.15.4 standard requires that several frequency tolerances be kept within 40 ppm accuracy. this means that a total offset up to 80 ppm between tran smitter and receiver will s till result in acceptable performance. the primary determini ng factor in meeting the 802.15.4 stan dard is the tolerance of the crystal oscillator referenc e frequency. a number of factors can cont ribute to this tolerance and a crystal specification will quantify each of them: 1. the initial (or make) tolerance of the crystal resonant frequency itself. 2. the variation of the crystal res onant frequency with temperature. 3. the variation of the crystal resonant frequency with time , also commonly known as aging. 4. the variation of the crystal re sonant frequency with load cap acitance, also commonly known as pulling. this is affected by: a) the external load capacitor values - init ial tolerance and variation with temperature b) the internal trim capacitor values - initial tolerance and variation with temperature c) stray capacitance on the crystal pin nodes - incl uding stray on-chip capaci tance, stray package capacitance and stray board capacitance; and its initial tolera nce and variation with temperature freescale has specified that a 16 mhz crystal with a <9 pf load capacitance is required. the 802.15.4 modem does not contain a reference divider, so 16 mhz is the only fre quency that can be used. a crystal requiring higher load capacitance is prohibited be cause a higher load on the amplifier circuit may compromise its performance. the crystal manufacturer de fines the load capacitance as that total external capacitance seen across the two term inals of the crystal. the oscillator amplifier configurat ion used in the 802.15.4 modem requires two balanced load capacitors from each terminal of the crystal to ground. as such, the capacitors are seen to be in series by the crystal, so each must be <18 pf for proper loading. the modem uses the 16 mhz crystal oscillator as the reference oscillator for the system and a programmable warp capabili ty is provided. it is c ontrolled by programming clko _ctl register 0a, bits 802.15.4 modem xtal1 xtal2 clko mc1321x 27 28 10 16mhz
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 23 15-8 (xtal_trim[ 7:0] ). the trimming procedure varies the fre quency by a few hertz pe r step, depending on the type of crystal. the high end of the frequency spectrum is set when xtal_trim[7 :0] is set to zero. as xtal_trim[7:0] is increased, the frequency is decr eased. accuracy of this feature can be observed by varying xtal_trim[ 7:0] and using a spectrum analyzer or fre quency counter to track the change in frequency of the crystal signal. the reference oscillator fr equency can be measured at the clko contact by programming clko_ctl register 0a, bits 2-0, to value 000. figure 13 shows typical oscillator frequenc y decrease versus the value programmed in xtal_trim[7:0]. figure 13. crystal frequency variation vs. xtal_trim[7:0] 4.8 radio usage the mc1321x rf analog interface has been designed to provide maximum flexibility as well as low external part count and cost. an on-chip transmit/recei ve (t/r) switch with bias switch (ct_bias) can be used for a simple single antenna in terface with a balun. al ternately, separate full differential rfin and pao outputs can be utilized for separate rx and tx antennae or external lna and pa designs. figure 14 shows three possible configurations for the transceiver radio rf usage. 1. figure 14a shows a single antenna configuration in which the mc1321x internal t/r switch is used. the balun converts the single-ended antenna to differential signals that interface to the rfin_x (pao_x) pins of the radio. the ct_bias pi n provides the proper bias point to the balun depending on operation, that is, ct_bias is at vdda voltage for transmit and is at ground for receive. the internal t/r switch enables the signa l to an onboard lna for receive and enables the onboard pas for transmit. 2. figure 14b shows a single antenna configuration with an external low noise amplifier (lna) for greater range. an external antenna switch is used to multiplex the antenna between receive and transmit. an lna is in the receive path to add gain for greater receive sensitivity. two external baluns are required to convert th e single-ended antenna switch signa ls to the differential signals -900 -800 -700 -600 -500 -400 -300 -200 -100 0 0 50 100 150 200 250 300 xtal_trim[7:0] (decimal) frequency decrease (hz)
mc13211/212/213 technical data, rev. 1.2 24 freescale semiconductor required by the radio. separate rf in and pao signals are provided for connection with the baluns, and the ct_bias signal is programmed to provide the external sw itch control. the polarity of the external switch control is selectable. 3. figure 14c shows a dual antenna configuration where th ere is a rx antenna and a tx antenna. for the receive side, the rx antenna is ac-coupled to the differenti al rfin inputs and these capacitors along with inductor l1 form a matching network. i nductors l2 and l3 are ac-coupled to ground to form a frequency trap. for the transmit side, the tx antenna is connected to the differential pao outputs, and inductors l4 and l5 provide dc-biasing to vdda but are ac isolated. figure 14. using the mc1321x with external rf components balun bypass rfin_p (pao_p) rfin_m (pao_m) ct_bias pao_p pao_m mc1321x l1 balun bypass rfin_p (pao_p) rfin_m (pao_m) ct_bias (a nt s w c tl) pao_p pao_m mc1321x lna ant sw balun vdd vdda bypass l1 14a) using onboard t/r switch 14b) using external ante nna switch with lna rfin_p (pao_p) rfin_m (pao_m) ct_bias pao_p pao_m mc1321x vdda tx antenna bypass bypass l1 l2 l3 l4 l5 rx antenna 14c) using dual antennae
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 25 5mcu 5.1 mcu block diagram figure 15. mcu block diag ram (hcs08, version a) ptd3 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 vss vdd pte3/miso pte2/ss pta7/kbi1p7? pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1 ptd0 ptc7 ptc6 ptc5 ptc4 ptc3/scl1 ptc2/sda1 port a port c port d port e 8-bit keyboard interrupt module (kbi1) iic module (iic) user flash user ram (4096 bytes max) debug module (dbg) (61,268 bytes max) mcu core 1-channel timer/pwm module (tpm1) ptb7/ad1p7? port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) mcu system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset vssad vddad vrefh vrefl analog-to-digital converter (atd1) interface module (sci1) serial communications 4-channel timer/pwm module (tpm2) port f ptd7/tpm2ch4 8 pta0/kbi1p0 8 ptb0/ad1p0 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g 10-bit cpu bdc notes 1. all port f and port g signals are present on the mcu, but only the signals used by the mc1321x are designated. for lowest power operation, all unused i/o should be programmed as outputs during initialization. timer channels are limited as noted due to use of port d i/o for internal signals. 2. dedicated serial peripheral interface module (spi) irq see note 1. see note 1.
mc13211/212/213 technical data, rev. 1.2 26 freescale semiconductor 5.2 mcu modes of operation the mcu has multiple operational modes to facilitate maximum system performa nce while also providing low-power modes. in the mc1321x, the mcu can use the following modes: ?run ?wait ?stop2 ?stop3 note the mcu can also be programmed for stop1 mode, but this mode is not usable. the reset to the modem func tion is controlled by an mcu gpio and the gpio state must be mainta ined during the mcu ?stop? condition. stop1 mode does not control i/o st ates as required during modem power down condition. 5.2.1 run mode this is the normal operating mode for the hcs08. this mode is selected when the bkgd/ms pin is high at the rising edge of reset. in this mode, the cpu executes code from internal memory with execution beginning at the address fetched from memory at $fffe:$ffff after reset. 5.2.2 wait mode wait mode is entered by executing a wait instruction. upon execution of the wait instruction, the cpu enters a low-power state in which it is not clocked. the i bit in ccr is cleared when the cpu enters the wait mode, enabling interrupts. when an interrupt request occurs, the cpu exits the wait mode and resumes processing, beginning with the stacking opera tions leading to the in terrupt service routine. while the mcu is in wait mode, there are some restrictions on which background debug commands can be used. only the background co mmand and memory-access-with-s tatus commands are available when the mcu is in wait mode. the memory-access- with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from wait mode and enter active background mode. 5.2.3 stop 2 the stop2 mode provides very low standby power consumption and main tains the contents of ram and the current state of all of the i/o pins. stop2 can be entered only if the lvd circuit is no t enabled in stop modes (either lvde or lvdse not set). before entering stop2 mode, the user must save the conten ts of the i/o port register s, as well as any other memory-mapped registers they want to restore after exit of stop2, to locations in ram. upon exit of stop2, these values can be restored by user software before pin latches are opened.
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 27 when the mcu is in stop2 mode, all internal circu its that are powered from the voltage regulator are turned off, except for the ram. the voltage regulator is in a low-power standby st ate, as is the atd. upon entry into stop2, the states of the i/ o pins are latched. the states are held while in stop2 mode and after exiting stop2 mode until a 1 is written to ppdack in spmsc2. exit from stop2 is performed by assertin g either of the wake-up pins: reset or irq, or by an rti interrupt. irq is always an active low input when the mcu is in stop2, regardless of how it was configured before entering stop2. upon wake-up from stop2 mode, the mc u will start up as from a power- on reset (por) except pin states remain latched. the cpu will take th e reset vector. the system and all pe ripherals will be in their default reset states and must be initialized. after waking up from stop2, the ppdf bit in spmsc2 is set. this flag may be used to dir ect user code to go to a stop2 recovery routine. ppdf remains set and the i/o pin states remain latc hed until a 1 is written to ppdack in spmsc2. to maintain i/o state for pins that were configured as general-purpose i/o, the user must restore the contents of the i/o port registers, which have been saved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restor ed from ram before writing to ppdack, then the register bits will assume their rese t states when the i/o pin latches are opened and the i/o pins will switch to their reset states. for pins that were configured as peripheral i/o, the user must reconfigure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. a separate self-clocked source (approximately 1 khz) for the real-time interrupt allows a walk-up from stop2 or stop3 modes with no external components. when rtis2:rtis1:rtis0 = 0:0:0, the real-time interrupt function and this 1-khz s ource are disabled. powe r consumption is lower when the 1-khz source is disabled, but in that case the real-tim e interrupt cannot wake the mcu from stop. 5.2.4 stop3 upon entering the stop3 mode, all of the clocks in the mcu, including the oscillat or itself, are halted. the icg is turned off, the atd is disabl ed, and the voltage regulator is put in standby. the states of all of the internal registers and logic, as well as the ram content, ar e maintained. the i/o pin states are not latched at the pin as in stop2. instead they are maintained by vi rtue of the states of the internal logic driving the pins being maintained. exit from stop3 is perf ormed by asserting reset , an asynchronous interrupt pi n, or through the real-time interrupt. the asynchronous interrupt pins are the irq or kbi pins. if stop3 is exited by means of the reset pin, then the mcu will be reset and operation will resume after taking the reset vector. exit by means of an asynchronous interrupt or the real-time interrupt will result in the mcu taking the appropriate interrupt vector.
mc13211/212/213 technical data, rev. 1.2 28 freescale semiconductor a separate self-clocked source (approximately1 khz) fo r the real-time interrupt allows a wake up from stop2 or stop3 modes with no external components. when rtis2:rtis1:rtis0 = 0:0:0, the real-time interrupt function and this 1-khz s ource are disabled. powe r consumption is lower when the 1-khz source is disabled, but in that case the real-tim e interrupt cannot wake the mcu from stop. 5.3 mcu memory as shown in figure 16 , on-chip memory in the mc1321x series of mcus consists of ram, flash program memory for non-volatile data storage, plus i/ o and control/status regi sters. the registers are divided into three groups: ? direct-page registers ($0000 through $007f) ? high-page registers ($1800 through $182b) ? nonvolatile registers ($ffb0 through $ffbf) figure 16. mc1321x memory maps direct page registers ram flash high page registers flash 4096 bytes 1920 bytes 59348 bytes $0000 $007f $0080 $107f $1800 $17ff $182b $182c $ffff $1080 direct page registers ram high page registers flash 32768 bytes $0000 $007f $0080 $087f $1800 $17ff $182b $182c $ffff $0880 2048 bytes unimplemented 26580 bytes unimplemented 3968 bytes $8000 $7fff mc13213 mc13212 direct page registers high page registers flash 16384 bytes $0000 $007f $0080 $047f $1800 $17ff $182b $182c $ffff $0480 ram 1024 bytes unimplemented 42964 bytes unimplemented 4992 bytes $c000 $bfff mc13211
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 29 5.4 mcu internal clock generator (icg) the icg provides multiple options for mcu clock sour ces. this block along with the ability to provide the mcu clock form the modem offers a user great flexibility when making choices between cost, precision, current draw, and pe rformance. as seen in figure 17 , the icg consists of four functional blocks. ? oscillator block ? the oscillator block provides means for connecting an external crystal or resonator. two frequency ranges are software sel ectable to allow optimal start-up and stability. alternatively, the oscillator block can be used to route an external square wave to the mcu system clock. external sources such as the modem clko output can provide a low cost source or a very precise clock source. the oscillator is capable of being configured for low power mode or high amplitude mode as selected by hgo. ? internal reference generator ? the internal reference genera tor consists of two controlled clock sources. one is desi gned to be approximately 8 mhz and can be selected as a local clock for the background debug controller. the other internal reference clock sour ce is typically 243 khz and can be trimmed for fi ner accuracy via soft ware when a precise timed ev ent is input to the mcu. this provides a highly reliable, low-cost clock source. ? frequency-locked loop ? a frequency-locked loop (fll) st age takes either the internal or external clock source and multiplies it to a highe r frequency. status bits provide information when the circuit has achieved lock and when it falls out of lock. additionally, this block can monitor the external reference clock and signals whether the clock is valid or not. ? clock select block ? the clock select block provides several switch options for connecting different clock sour ces to the system clock tree. icgdclk is the multiplied clock frequency out of the fll, icgerclk is the reference clock fre quency from the crystal or external clock source, and ffe (fixed frequency enable) is a control si gnal used to control the system fixed frequency clock (xclk). icglclk is the clock source for the background debug controller (bdc). the module is intended to be very us er friendly with many of the featur es occurring automatically without user intervention. 5.4.1 features features of the icg and clock distribution system: ? several options for the mcu pr imary clock source allow a wide range of cost, frequency, and precision choices: ? 32 khz?100 khz crystal or resonator ? 1 mhz?16 mhz crystal or resonator ? external clock supplied by modem clko or other source ? internal reference generator ? defaults to self-clocked mode to minimize startup delays ? frequency-locked loop (fll) generates 8 mhz to 40 mhz (for bus rates up to 20 mhz). when using modem clko as external source, maximu m fll frequency is 32 mhz (16 mhz bus rate) with clko = 16 mhz or maximum fll frequency is 40 mhz (20 mhz bus rate) with clko = 4 mhz.
mc13211/212/213 technical data, rev. 1.2 30 freescale semiconductor ? uses external or internal clock as reference frequency ? automatic lockout of non-running clock sources ? reset or interrupt on loss of clock or loss of fll lock ? digitally-controlled oscillator (dco) preserves previous fre quency settings, allowing fast frequency lock when re covering from stop3 mode ? dco will maintain operating fre quency during a loss or removal of reference clock. when fll is engaged (fee or fei) loss of lock or loss of clock adds a divide-by-2 to icg to prevent over-clocking of the system. ? post-fll divider selects 1 of 8 bus rate divisors (/1 through /128) ? separate self-clocked s ource for real-time interrupt ? trimmable internal clock so urce supports sci communications without additional external components ? automatic fll engagement after lock is acquired ? selectable low-power/high- gain oscillator modes 5.4.2 modes of operation this section provides a high-level description only. ? mode 1 ? off the output clock, icgout, is static. this mode may be entered when the stop instruction is executed. ? mode 2 ? self-clocked (scm) default mode of operation that is entered out of reset. the icg?s fll is open l oop and the digitally controlled oscillator (dco) is free running at a frequency set by the filter bits. ? mode 3 ? fll engaged internal (fei) in this mode, the icg?s fll is used to create frequencies that ar e programmable mu ltiples of the internal reference clock. ? fll engaged internal unlocked is a transition state which occurs while the fll is attempting to lock. the fll dco frequency is off target and the fll is adjusting the dco to match the target frequency. ? fll engaged internal locked is a state which occurs when the fll detects that the dco is locked to a multiple of the internal reference. ? mode 4 ? fll bypassed external (fbe) in this mode, the icg is configur ed to bypass the fll and use an ex ternal clock as the clock source. ? mode 5 ? fll engaged external (fee) the icg?s fll is used to generate frequencies that are programmable multiples of the external clock reference. ? fll engaged external unlocked is a transition state which occurs while the fll is attempting to lock. the fll dco frequency is off target and the fll is adjusting the dco to match the target frequency.
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 31 ? fll engaged external locked is a state which occurs when the fll detects that the dco is locked to a multiple of the internal reference. figure 17 is a top-level diagram that shows the functiona l organization of the in ternal clock generation (icg) module. figure 17. icg block diagram 5.5 central processing unit (cpu) the hcs08 cpu is fully source- and object-code -compatible with the m68hc08 cpu. several instructions and enhanced addressi ng modes were added to improve c compiler efficiency and to support a new background debug system which replaces the m onitor mode of earlier m68hc08 microcontrollers (mcu). 5.5.1 cpu features features of the cpu include: ? object code fully upward-compatible with m68hc05 a nd m68hc08 families ? all registers and memory are mappe d to a single 64-kbyte address space ? 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) ? 16-bit index register (h:x) with powerful indexed addressing modes ? 8-bit accumulator (a) ? many instructions treat x as a second general-purpose 8-bit register ? seven addressing modes: oscillator (osc) frequency internal ptg2/extal ptg1/xtal reference generators clock select 8 mhz irg loss of lock and clock detector locked loop (fll) fixed clock select icgout typ 243 khz rg icglclk icg ffe vdd vss dco with external ref select ref select local clock for optional use with bdc output clock select icgdclk /r icgerclk icgirclk
mc13211/212/213 technical data, rev. 1.2 32 freescale semiconductor ? inherent ? operands in internal registers ? relative ? 8-bit signed offset to branch destination ? immediate ? operand in next object code byte(s) ? direct ? operand in memory at 0x0000?0x00ff ? extended ? operand anywhere in 64-kbyte address space ? indexed relative to h:x ? five submodes including auto increment ? indexed relative to sp ? impr oves c efficiency dramatically ? memory-to-memory data move instructions with four address mode combinations ? overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ? efficient bit manipulation instructions ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? stop and wait instructions to invoke low-power operating modes 5.5.2 programmer?s mo del and cpu registers figure 18 shows the five cpu registers. cpu regi sters are not part of the memory map. figure 18. cpu registers sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11h i nz
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 33 5.6 parallel input/output the mc1321x hcs08 has seven i/o ports which include a total of 56 gene ral-purpose i/o si gnals (one of these pins, ptg0, is output only) . the mc1321x family does not use all the these signals as denoted in figure 15 . port f and part of port g ar e not utilized. the mc1321x family ma kes use of the remaining i/o as pinned-out i/o or as internally dedicat ed signal for communication with the 802.15.4 modem. as stated above port f and part of port g are not utilized. these signals and any unused io should be programmed as outputs during initialization for lowest power operatio n. many of these pins are shared with on-chip peripherals such as timer systems, various communication ports, or keyboard interrupts. when these other modules are not cont rolling the port pins, th ey revert to general-purpose i/o control. for each i/o pin, a port data bit provides access to input (read) and output (write) da ta, a data direction bit controls the direction of th e pin, and a pullup enable bi t enables an internal pull up device (provided the pin is configured as an input), and a slew rate control bit controls the rise and fall times of the pins.parallel i/o features include: ? a total of 32 general-purpose i/o pins in seven ports (ptg0 is output only) ? high-current drivers on port c ? hysteresis input buffers ? software-controlled pu llups on each input pin ? software-controlled sl ew rate output buffers ? eight port a pins shared with kbi1 ? eight port b pins shared with atd1 ? eight high-current port c pins shared with sci2 and iic1 ? eight port d pins shared with tpm1 and tpm2 ? eight port e pins shared with sci1 and spi1 ? eight port g pins shared wi th extal, xtal, and bkgd/ms note not all port g signals and no port f si gnals are bonded out, but are present in the mcu hardware (see figure 15 ). these port i/o signals should be programmed as outputs set to the low state. 5.7 mcu peripherals 5.7.1 modem dedicated serial pe ripheral interface (spi) module the hcs08 provides one serial peri pheral interface (spi) module which is connected within the sip to the modem spi port. the four pins asso ciated with spi functionality are shared with port e pins 2?5. when the spi is enabled, the direction of pins is controlled by module configuration. the mcu spi port is used only in master mode on the mc1321x family. the user must program the spi module for the proper characteristi cs as listed in the features below and also program the ss signal to have the proper use to support the modem tr ansaction protocol for the modem ce signal.
mc13211/212/213 technical data, rev. 1.2 34 freescale semiconductor 5.7.1.1 spi features features of the spi module use include: ? used in master mode only ? programmable transmit bit rate (maxim um usable rate is 8 mhz with modem) ? double-buffered transmit and receive ? serial clock phase and polarity option must be programmed to cpha = 0 and cpol = 0 ? programmable slave select output to support modem spi protocol ? msb-first data transfer 5.7.1.2 spi module block diagram figure 19 is a block diagram of the spi module. the central element of th e spi is the spi shift register. data is written to the double-buffere d transmitter (write to spi1d) and gets transferred to the spi shift register at the start of a data transfer. after shifting in a byte of data, the data is transferred into the double-buffered receiver wh ere it can be read (read from spi1d ). pin multiplexing logic controls connections between mcu pins and the spi module. when the spi is configured as a master, the clock out put is routed to the spsc k pin, the shifter output is routed to mosi, and the shifter i nput is routed from the miso pin. figure 19. modem dedicated spi block diagram spi shift register shift clock shift direction rx buffer full tx buffer empty shift out shift in enable spi system clock logic clock generator bus rate clock master/slave mode select mode fault detection master clock slave clock spi interrupt request pin control m s master/ slave mosi miso spsck ss m s s m modf spe lsbfe mstr sprf sptef sptie spie mod- ssoe spc0 bidiroe spibr tx buffer (write rx buffer (read) mosi miso spiclk ce modem spi port connected onboard sip
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 35 5.7.2 keyboard interrupt (kbi) module the hcs08 has one kbi module with eight keyboa rd interrupt inputs that share port a pins. the kbi module allows up to eight pins to act as add itional interrupt sources. f our of these pins allow falling-edge sensing while the other four can be configured for either rising-edge sensing or falling-edge sensing. the sensing mode fo r all eight pins can also be modified to detect edges and levels instead of only edges. this on-chip peripheral module is called a keyboard interrupt (kbi) module because originally it was designed to simplify the connection and use of row-column matrices of keyboard switches. however, these inputs are also useful as extra external interrupt inputs and as an external means of waking up the mcu from stop or wait low-power modes. 5.7.3 kbi features the keyboard interrupt (kbi ) module features include: ? keyboard interrupts selectable on eight port pins: ? four falling-edge/low-level sensitive ? four falling-edge/low-level or rising-edge/high-level sensitive ? choice of edge-only or edge-and-level sensitivity ? common interrupt flag and interrupt enable control ? capable of waking up the mcu from stop3 or wait mode 5.7.3.1 kbi block diagram figure 20 shows the block diagram for the kbi module. figure 20. kbi block diagram keyboard interrupt dq ck clr vdd kbimod kbie keyboard interrupt ff request kback reset synchronizer kbf stop bypass stop busclk kbipen 0 1 s kbedgn kbipe0 kbipe3 kbipe4 0 1 s kbedg4 kbip0 kbip3 kbip4 kbipn
mc13211/212/213 technical data, rev. 1.2 36 freescale semiconductor 5.7.4 timer/pwm (tpm) module introduction the hcs08 includes two independe nt timer/pwm (tpm) modules wh ich support traditional input capture, output compare, or buffe red edge-aligned pulse-width modul ation (pwm) on each channel. a control bit in each tpm conf igures all channels in that timer to operate as center-a ligned pwm functions. in each of these two tpms, timing functions are base d on a separate 16-bit counter with prescaler and modulo features to control frequency and range (peri od between overflows) of th e time reference. this timing system is ideally suited fo r a wide range of control appli cations, and the center-aligned pwm capability on the 3-channel tpm extends the field of applications to motor control in small appliances. the use of the fixed system clock, xclk, as the cloc k source for either of th e tpm modules allows the tpm prescaler to run using the oscillator rate divi ded by two (icgerclk/2). th is clock source must be selected only if the icg is configured in either fbe or fee mode. in fbe mode, this selection is redundant because the busclk frequency is the same as xclk. in fee mode, the proper conditions must be met for xclk to equal icgerclk/2. sele cting xclk as the clock source with the icg in either fei or scm mode will result in the tpm being non-functional. 5.7.4.1 tpm features the timer system in the mc1321x family mcu incl udes a 1-channel tpm1 and a separate 4-channel tpm2. timer system features include: ? a total of 5 channels: ? each channel may be input capture, output compare, or buffered edge-aligned pwm ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? selectable polarity on pwm outputs ? each tpm may be configured fo r buffered, center-aligned pulse-w idth modulation (cpwm) on all channels ? clock source to prescaler for each tpm is inde pendently selectable as bus clock, fixed system clock, or an external pin ? prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 ? 16-bit free-running or up/ down (cpwm) count operation ? 16-bit modulus register to control counter range ? timer system enable ? one interrupt per channel pl us terminal count interrupt 5.7.4.2 tpm block diagram the tpm uses one input/output (i/o) pin per chan nel, tpmxchn where x is the tpm number (for example, 1 or 2) and n is the channel number (for example, 1?4). the tpm sh ares its i/o pins with general-purpose i/o port pins. figure 21 shows the structure of a tpm. some mcus include more than one tpm, with various numbers of channels.
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 37 figure 21. tpm block diagram 5.7.5 serial communications interface (sci) module the hcs08 includes two independent serial communications interface (sci) modules ? sometimes called universal asynchronous receiver/transmitters (uarts). typically, th ese systems are used to connect to the rs232 serial input/output (i/o ) port of a personal computer or workst ation, and they can also be used to communicate with other embedded controllers. a flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard baud rates beyond 115.2 kbaud. transmit and receive within the same sci use a common baud ra te, and each sci module has a separate baud rate generator. this sci system offers many advanced features not commonly found on other asynchronous serial i/o peripherals on other embedded cont rollers. the receiver employs an advanced data sampling technique that ensures reliable communicati on and noise detection. hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. 5.7.5.1 sci features features of sci module include: ? full-duplex, standard non-re turn-to-zero (nrz) format ? double-buffered transmitter and r eceiver with separate enables ? programmable baud rates (13-bit modulo divider) ? interrupt-driven or polled operation: ? transmit data register em pty and transmission complete ? receive data register full prescale and select 16-bit comparator main 16-bit counter 16-bit comparator 16-bit latch port channel 1 logic interrupt counter reset divide by clock source off, bus, xclk, ext busclk xclk select sync interrupt 1, 2, 4, 8, 16, 32, 64, or 128 logic logic clksa clksb ps2 ps1 ps0 cpwms tfie tof els1a ch1f els1b ch1ie ms1b ms1a tpm1modh:tpm1modl tpm1) ext clk tpm1c1vh:tpm1c1v tpm1ch1
mc13211/212/213 technical data, rev. 1.2 38 freescale semiconductor ? receive overrun, parity error, framing erro r, and noise error ? idle receiver detect ? hardware parity generation and checking ? programmable 8-bit or 9-bit character length ? receiver walk-up by idle-line or address-mark 5.7.5.2 sci block diagrams the sci allows full-duplex, as ynchronous, nrz serial communica tion among the mcu and remote devices, including other mcus . the sci comprises a baud rate generato r, transmitter, and receiver block. the transmitter and receiver opera te independently, although they use the same baud rate generator. during normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. figure 22 and figure 23 show the sci transmitter and receiver block diagrams. figure 22. sci transmitter h 8 7 6 5 4 3 2 1 0 l scid ? tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) enable sci controls txd1 txd1 direction to txd1 pin logic loop control to receive data in to txd1 pin tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scixd
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 39 figure 23. sci receiver h 8 7 6 5 4 3 2 1 0 l scid ? rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd1 pin rate clock rx interrupt request data recovery divide 16 baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc wake ilt rwu m
mc13211/212/213 technical data, rev. 1.2 40 freescale semiconductor 5.7.6 inter-integrated circuit (iic) module the hcs08 microcontroller provides one inter-integr ated circuit (iic) module for communication with other integrated circuits. the two pins associated wi th this module, sda and scl share port c pins 2 and 3, respectively. all functionality as described in th is section is available on hcs08. when the iic is enabled, the direction of pins is controlled by module configuration. if the iic is disabled, both pins can be used as general-purpose i/o. the inter-integrated circuit (iic) provides a method of communication between a number of devices{statement}. the inte rface is designed to ope rate up to 100 kbps with maximum bus loading and timing. the device is capabl e of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communica tion length and the number of devi ces that can be connected are limited by a maximum bus capacitance of 400 pf. 5.7.6.1 iic features the iic includes these features: ? ip bus v2.0 compliant compa tible with iic bus standard ? multi-master opera tion {statement} ? software programmable for one of 64 different serial clock frequencies {iic_prescale.asm} ? software selectable acknow ledge bit {iic_ack.asm} ? interrupt driven byte-by-byte data transfer {iic_int.asm} ? arbitration lost interrupt with automatic mode switching from master to slave {iic_int.asm} ? calling address identificati on interrupt {iic_int.asm} ? start and stop signal generation/detection {iic_transmit.asm }{iic_receive.asm}{i ic_receive_addon.asm} ? repeated start signal generation {iic_transmit.asm} ? acknowledge bit generation/ detection {iic_ack.asm} ? bus busy detection {iic_bus_busy.asm} 5.7.6.2 iic modes of operation the iic functions the same in normal and monitor m odes. a brief description of the iic in the various mcu modes is given here. run mode this is the basic mode of operation. to conserve power in this mode, disable the module. wait mode the module will continue to operate while the mcu is in wait mode and can provide a wake-up interrupt. stop mode the iic is inactive in stop3 mode for reduced power consumption. the stop instruction does not affect iic register states. stop1 and stop2 will reset the register contents.
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 41 5.7.6.3 iic block diagram figure 24 shows a block diagram of the iic module. figure 24. iic functional block diagram input sync in/out data shift register address compare interrupt clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl sda address
mc13211/212/213 technical data, rev. 1.2 42 freescale semiconductor 5.7.7 analog-to-digital (atd) module the hcs08 provides one 8-channel analog-to-digita l (atd) module. the eight atd channels share port b. each channel individually can be configur ed for general-purpose i/o or for atd functionality. 5.7.7.1 atd features ? 8-/10-bit resolution ? 14.0 sec, 10-bit single convers ion time at a conversion frequency of 2 mhz ? left-/right-justified result data ? left-justified signed data mode ? conversion complete flag or convers ion complete interrupt generation ? analog input multiplexer for up to eight analog input channels ? single or continuous conversion mode 5.7.7.2 atd modes of operation the atd has two modes for low power 1. stop mode 2. power-down mode 5.7.7.2.1 atd stop mode when the mcu goes into stop mode, the mcu stops th e clocks and the atd analog circuitry is turned off, placing the module into a low- power state. once in stop mode, th e atd module aborts any single or continuous conversion in progress. upon exiting stop mode, no conversions occur and the registers have their previous values. as long as the atdpu bit is set prior to entering stop mode, the module is reactivated coming out of stop. 5.7.7.2.2 atd power down mode clearing the atdpu bit in register atd1c also pla ces the atd module in a low-power state. the atd conversion clock is disabled and the analog circuitr y is turned off, placing the module in power-down mode. (this mode does not remove power to the atd module.) once in power-down mode, the atd module aborts any conversion in pr ogress. upon setting the atdpu bit, the module is reactivated. during power-down mode, the atd regi sters are still accessible. note the reset state of the atdpu bit is zer o. therefore, the module is reset into the power-down state.
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 43 5.7.7.3 atd block diagram figure 25 shows the functional structure of the atd module. figure 25. atd block diagram address control r/w data ctl data justification interrupt conversion register sar_reg <9:0> conversion clock prescaler busclk clock prescaler ctl status state machine conversion mode control block control and registers ctl result registers input mux = internal pins = chip pads vddad vss vssad vdd ad1p0 ad1p1 ad1p2 ad1p3 ad1p4 ad1p5 ad1p6 ad1p7 vrefl vrefh analog digital powerdown successive approxi mation register analog-to-digital converter (atd) block status
mc13211/212/213 technical data, rev. 1.2 44 freescale semiconductor 5.7.8 development support development support systems in the include the background debug controller (bdc) and the on-chip debug module (dbg). the bd c provides a single-wire debug interface to the targ et mcu that provides a convenient interface for programmi ng the on-chip flash and other non- volatile memories. the bdc is also the primary debug interface for development a nd allows non-intrusive access to memory data and traditional debug features such as cpu register modify, breakpoints, and single instruction trace commands. address and data bus signals are not available on external pins (not ev en in test modes). debug is done through commands fed into the mcu via the singl e-wire background debug interface. the debug module provides a means to selectively trigge r and capture bus information so an external development system can reconstruct what happened inside th e mcu on a cycle-by-cycle basis wit hout having external access to the address and data signals. the alternate bdc clock source for hcs08 is the icglclk. 5.7.8.1 development support features features of the background de bug controller (bdc) include: ? single pin for mode selecti on and background communications ? bdc registers are not located in the memory map ? sync command to determine target communications rate ? non-intrusive commands for memory access ? active background mode comma nds for cpu register access ? go and trace1 commands ? background command can wake cpu from stop or wait modes ? one hardware address br eakpoint built into bdc ? oscillator runs in stop mode, if bdc enabled ? cop watchdog disabled while in active background mode features of the debug module (dbg) include: ? two trigger comparators: ? two address + read/write (r/w) or ? one full address + data + r/w ? flexible 8-word by 16-bit fi fo (first-in, first-out) buffe r for capture information: ? change-of-flow addresses or ? event-only data ? two types of breakpoints: ? tag breakpoints for instruction opcodes ? force breakpoints for any address access ? nine trigger modes:
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 45 ? a-only ? a or b ? a then b ? a and b data (full mode) ? a and not b data (full mode) ? event-only b (store data) ? a then event-only b (store data) ? inside range (a address b) ? outside range (address < a or address > b) 6 system electrical specification this section details maximum ratings for the 71 pi n lga package and recomme nded operati ng conditions, dc characteristics, and ac character istics for the modem, and the mcu. 6.1 sip lga package maximum ratings absolute maximum ratings are stre ss ratings only, and func tional operation at the maximum rating is not guaranteed. stress beyond the limits specified in table 6 may affect device reliabi lity or cause permanent damage to the device. for functiona l operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appr opriate logic volta ge level (for instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table 6 shows the maximum ratings for the 71 pin lga package. table 6. lga package maximum ratings rating symbol value unit maximum junction temperature t j 125 c storage temperature range t stg -55 to 125 c power supply voltage v batt , v ddint -0.3 to 3.6 vdc digital input voltage vin -0.3 to (v ddint + 0.3) rf input power p max 10 dbm maximum current into v dd i dd 120 ma instantaneous maximum current (single pin limit) 1 , 2 , 3 i d 25 ma note: maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics or recommended operating conditions tables. note: meets human body model (hbm) = 2 kv. rf input/output pins have no esd protection.
mc13211/212/213 technical data, rev. 1.2 46 freescale semiconductor 6.2 802.15.4 modem electrical characteristics 6.2.1 modem recommended operating conditions 1 input must be current limited to the value specified. to dete rmine the value of the required cu rrent-limiting resistor, calcula te resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection curren t may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. table 7. recommended operating conditions characteristic symbol min typ max unit power supply voltage (v batt = v ddint ) 1 1 if the supply voltage is produced by a s witching dc-dc converter, ripple should be less than 100 mv peak-to-peak. v batt, v ddint 2.0 2.7 3.4 vdc input frequency f in 2.405 - 2.480 ghz operating temperature range t a -40 25 85 c logic input voltage low v il 0 - 30% v ddint v logic input voltage high v ih 70% v ddint -v ddint v spi clock rate f spi --8.0mhz rf input power p max --10dbm crystal reference oscillator frequency (40 ppm over operating conditions to meet the 802.15.4 standard.) f ref 16 mhz only
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 47 6.2.2 modem dc electr ical characteristics 6.2.3 modem ac electr ical characteristics note all ac parameters measured with spi registers at defaul t settings except where noted. table 8. dc electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, unless otherwise noted) characteristic symbol min typ max unit power supply current (v batt + v ddint ) off 1 hibernate 1 doze (no clko) 1 2 idle transmit mode (0 dbm nominal output power) receive mode 1 to attain specified low power current, all gpio and other digital io must be handled properly. see section 7.2, ?low power considerations . 2 clko frequency at default value of 32.786 khz. i leakage i cch i ccd i cci i cct i ccr - - - - - - 0.2 1.0 35 500 30 37 1.0 6.0 102 800 35 42 a a a a ma ma input current (v in = 0 v or v ddint ) (all digital inputs) i in --1 a input low voltage (all digital inputs) v il 0-30% v ddint v input high voltage (all digital inputs) v ih 70% v ddint -v ddint v output high voltage (i oh = -1 ma) (all digital outputs) v oh 80% v ddint -v ddint v output low voltage (i ol = 1 ma) (all digital outputs) v ol 0-20% v ddint v table 9. receiver ac electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, f ref = 16 mhz, unless otherwise noted.) characteristic symbol min typ max unit sensitivity for 1% packet error rate (per) (-40 to +85 c) sens per --92-dbm sensitivity for 1% packet error rate (per) (+25 c) - -92 -87 dbm saturation (maximum input level) sens max -10-dbm channel rejection for 1% per (desired signal -82 dbm) +5 mhz (adjacent channel) -5 mhz (adjacent channel) +10 mhz (alternate channel) -10 mhz (alternate channel) >= 15 mhz - - - - - 34 29 44 44 46 - - - - - db db db db db
mc13211/212/213 technical data, rev. 1.2 48 freescale semiconductor figure 26. rf parametric evaluation circuit frequency error tolerance - - 200 khz symbol rate error tolerance - - 80 ppm table 10. transmitter ac electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, f ref = 16 mhz, unless otherwise noted.) characteristic symbol min typ max unit power spectral density (-40 to +85 c) absolute limit - -47 - dbm power spectral density (-40 to +85 c) relative limit - 47 - nominal output power 1 1 spi register 12 is default value of 0x00bc whic h sets output power to nominal (-1 dbm typical). p out -4 -1 2 dbm maximum output power 2 2 spi register 12 programmed to 0xff which sets output power to maximum. 3dbm error vector magnitude evm - 18 35 % ouput power control range - 30 - db over the air data rate - 250 - kbps 2nd harmonic 3 3 measurements taken at output of eval uation circuit set for maximum power out. --43-dbc 3rd harmonic 3 --45-dbc table 9. receiver ac electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, f ref = 16 mhz, unless otherwise noted.) characteristic symbol min typ max unit 5 1 6 2 3 4 z4 ldb212g4005c-001 l10 4.7nh l11 4.7nh c12 10pf vdda vdd 6 in 5 vcont 4 out1 1 out2 3 gnd 2 ic2 pg2012tk-e2 c13 10pf c14 10pf 5 1 6 2 3 4 z5 ldb212g4005c-001 l12 2.2nh c15 1.8pf 1 2 5 3 4 j3 sma_edge_recep t l13 3.3nh l14 3.3nh c16 10pf c17 1.0pf c18 1.8pf gpio1 44 pao_m 39 pao_p 38 rfin_p 36 rfin_m 35 ct_bias 34 u4 mc1321x
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 49 6.3 mcu electrical characteristics 6.3.1 mcu dc characteristics table 11. mcu dc characteristics (temperature range = ?40 to 85 c ambient) parameter symbol min typical 1 max unit supply voltage (run, wait and stop modes.) 0 < f bus < 8 mhz 0 < f bus < 20 mhz v dd 1.8 2.08 3.6 3.6 v minimum ram retention supply voltage applied to v dd v ram 1.0 2 ?v low-voltage detection threshold ? high range (v dd falling) (v dd rising) v lvdh 2.08 2.16 2.1 2.19 2.2 2.27 v low-voltage detection threshold ? low range (v dd falling) (v dd rising) v lvdl 1.80 1.88 1.82 1.90 1.91 1.99 v low-voltage warning threshold ? high range (v dd falling) (v dd rising) v lvwh 2.35 2.35 2.40 2.40 2.5 v low-voltage warning threshold ? low range (v dd falling) (v dd rising) v lvwl 2.08 2.16 2.1 2.19 2.2 2.27 v power on reset (por ) re-arm voltage (2) mode = stop mode = run and wait v rearm 0.20 0.50 0.30 0.80 0.40 1.2 v input high voltage (v dd > 2.3 v) (all digital inputs) v ih 0.70 v dd ?v input high voltage (1.8 v v dd 2.3 v) (all digital inputs) v ih 0.85 v dd ? v input low voltage (v dd > 2.3 v) (all digital inputs) v il ? 0.35 v dd v input low voltage (1.8 v v dd 2.3 v) (all digital inputs) v il ? 0.30 v dd v input hysteresis (all digital inputs) v hys 0.06 v dd ?v input leakage current (per pin) v in = v dd or v ss, all input only pins |i in | ? 0.025 1.0 a high impedance (off-state) leakage current (per pin) v in = v dd or v ss , all input/output |i oz | ? 0.025 1.0 a internal pullup and pulldown resistors 3 (all port pins and irq) r pu 17.5 52.5 kohm internal pulldown resistors (port a4?a7 and irq) r pd 17.5 52.5 kohm
mc13211/212/213 technical data, rev. 1.2 50 freescale semiconductor output high voltage (v dd 1.8 v) i oh = ?2 ma (ports a, b, d, e, and g) v oh v dd ? 0.5 ? v output high voltage (ports c and f) i oh = ?10 ma (v dd 2.7 v) i oh = ?6 ma (v dd 2.3 v) i oh = ?3 ma (v dd 1.8 v) v dd ? 0.5 ? ? ? maximum total i oh for all port pins |i oht |? 60 ma output low voltage (v dd 1.8 v) i ol = 2.0 ma (ports a, b, d, e, and g) v ol ?0.5 v output low voltage (ports c and f) i ol = 10.0 ma (v dd 2.7 v) i ol = 6 ma (v dd 2.3 v) i ol = 3 ma (v dd 1.8 v) ? ? ? 0.5 0.5 0.5 maximum total i ol for all port pins i olt ?60ma dc injection current 4, 5, 6, 7, 8 v in < v ss , v in > v dd single pin limit total mcu limit, includes sum of all stressed pins |i ic | ? ? 0.2 5 ma ma input capacitance (all non-supply pins) (2) c in ?7pf 1 typicals are measured at 25 c. 2 this parameter is characterized and not tested on each device. 3 measurement condition for pull resistors: v in = v ss for pullup and v in = v dd for pulldown. 4 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. 5 all functional non-supply pins are internally clamped to v ss and v dd . 6 input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calcula te resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 this parameter is characterized and not tested on each device. 8 irq does not have a clamp diode to v dd . do not drive irq above v dd . table 11. mcu dc characteristics (continued) (temperature range = ?40 to 85 c ambient) parameter symbol min typical 1 max unit
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 51 6.3.2 mcu supply cu rrent characteristics table 12. mcu supply cu rrent characteristics (temperature range = ?40 to 85 c ambient) parameter symbol v dd (v) typical 1 max 2 temp. ( c) run supply current 3 measured at (cpu clock = 2 mhz, f bus = 1 mhz) ri dd 3 1.1 ma 2.1 ma (4) 2.1 ma (4) 2.1 ma (4) 55 70 85 2 0.8 ma 1.8 ma (4) 1.8 ma (4) 1.8 ma (4) 55 70 85 run supply current (3) measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 3 6.5 ma 7.5 ma (4) 7.5 ma (4) 7.5 ma (5) 55 70 85 2 4.8 ma 5.8 ma (4) 5.8 ma (4) 5.8 ma (4) 55 70 85 stop1 mode supply current s1i dd 3 25 na 0.6 a (4) 1.8 a (4) 4.0 a (5) 55 70 85 2 20 na 500 na (4) 1.5 a (4) 3.3 a (4) 55 70 85 stop2 mode supply current s2i dd 3 550 na 3.0 a (4) 5.5 a (4) 11 a (5) 55 70 85 2 400 na 2.4 a (4) 5.0 a (4) 9.5 a (4) 55 70 85 stop3 mode supply current s3i dd 3 675 na 4.3 a (4) 7.2 a (4) 17.0 a (5) 55 70 85 2 500 na 3.5 a (4) 6.2 a (4) 15.0 a (4) 55 70 85 rti adder to stop2 or stop3 6 3 300 na 55 70 85 2 300 na 55 70 85
mc13211/212/213 technical data, rev. 1.2 52 freescale semiconductor lvi adder to stop3 (lvdse = lvde = 1) 370 a 55 70 85 260 a 55 70 85 adder to stop3 for oscillator enabled 7 (oscsten = 1) 35 a 55 70 85 25 a 55 70 85 adder for loss-of-clock enabled 3 9 a 55 70 85 1 typicals are measured at 25 c. 2 values given here are preliminary estimates prior to completing characterization. 3 all modules except atd active, icg configured for fbe, and does not include any dc loads on port pins 4 values are characterized but not tested on every part. 5 every unit tested to this parameter. all other values in the max column are guaranteed by characterization. 6 most customers are expected to find that auto-wakeup from st op2 or stop3 can be used instead of the higher current wait mode. wait mode typical is 560 a at 3 v and 422 a at 2v with f bus = 1 mhz. 7 values given under the following conditions: low range o peration (range = 0), low power mode (hgo = 0), clock monitordisabled (locd = 1) table 12. mcu supply current characteristics (continued) (temperature range = ?40 to 85 c ambient) parameter symbol v dd (v) typical 1 max 2 temp. ( c)
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 53 6.3.3 mcu atd characteristics table 13. mcu atd electrical characteristics (operating) num characteristic condition symbol min typical max unit 1 atd supply 1 1 v ddad must be at same potential as v dd . v ddad 1.80 ? 3.6 v 2 atd supply current enabled i ddadrun ?0.71.2ma disabled (atdpu = 0 or stop) i ddadstop ? 0.02 0.6 a 3 differential supply voltage v dd ?v ddad |v ddlt | ? ? 100 mv 4 differential ground voltage v ss ?v ssad |v sdlt ? ? 100 mv 5 reference potential, low |v refl |? ? v ssad v reference potential, high 2.08v < v ddad < 3.6v v refh 2.08 ? v ddad v 1.80v < v ddad < 2.08v v ddad ?v ddad 6 reference supply current (v refh to v refl ) enabled i ref ? 200 300 a disabled (atdpu = 0 or stop) i ref ? <0.01 0.02 7 analog input voltage 2 2 maximum electrical operating range, not valid conversion range. v indc v ssad ? 0.3 ? v ddad + 0.3 v
mc13211/212/213 technical data, rev. 1.2 54 freescale semiconductor table 14. atd timing/perf ormance characteristics 1 1 all accuracy numbers are based on processor and system being in wait st ate (very little activity and no io switching) and that adequate low-pass filtering is presen t on analog input pi ns (filter with 0.01 f to 0.1 f capacitor between analog input and v refl ). failure to observe these gu idelines may result in system or microcontroller noise c ausing accuracy errors which will vary based on board layout and the type and magnitude of the activity. num characteristic symbol condition min typ max unit 1 atd conversion clock frequency f atdclk 2.08v < v ddad < 3.6v 0.5 ? 2.0 mhz 1.80v < v ddad < 2.08v 0.5 ? 1.0 2 conversion cycles (continuous convert) 2 2 this is the conversion time for subsequent conversions in continuous convert mode. actual conversion time for single conversions or the first conversion in continuous mode is extended by one atd clock cycle and 2 bus cycles due to starting the conversion and setting the ccf flag. the total c onversion time in bus cycles for a conversion is: sc bus cycles = ((p rs+1)*2) * (28+1) + 2 cc bus cycles = ((prs+1)*2) * (28) ccp 28 28 <30 atdclk cycles 3 conversion time t conv 2.08v < v ddad < 3.6v 14.0 ? 60.0 s 1.80v < v ddad < 2.08v 28.0 ? 60.0 4 source impedance at input 3 3 r as is the real portion of the impedance of the network driving the analog input pin. values greater than this amount may not fully charge the input circuitry of the atd resulting in accuracy error. r as ??10k ? 5 analog input voltage 4 4 analog input must be between v refl and v refh for valid conversion. values greater than v refh will convert to $3ff less the full scale error (e fs ). v ain v refl v refh v 6 ideal resolution (1 lsb) 5 5 the resolution is the ideal step size or 1lsb = (v refh ?v refl )/1024 res 2.08v < v ddad < 3.6v 2.031 ? 3.516 mv 1.80v < v ddad < 2.08v 1.758 ? 2.031 7 differential non-linearity 6 6 differential non-linearity is the difference between the curren t code width and the ideal code width (1lsb). the current code width is the difference in the transition voltages to and from the current code. dnl 1.80v < v ddad < 3.6v ? + 0.5 + 1.0 lsb 8 integral non-linearity 7 7 integral non-linearity is the difference be tween the transition voltage to the curre nt code and the adjusted ideal transition voltage for the current code. the adjusted ideal transition voltage is (current code?1/2)*(1/((v refh +e fs )?(v refl +e zs ))). inl 1.80 v < v ddad < 3.6v ? + 0.5 + 1.0 lsb 9 zero-scale error 8 8 zero-scale error is the difference between the transition to t he first valid code and the ideal transition to that code. the id eal transition voltage to a given code is (code?1/2)*(1/(v refh ?v refl )). e zs 1.80v < v ddad < 3.6v ? + 0.4 + 1.0 lsb 10 full-scale error 9 9 full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. the ide al transition voltage to a given code is (code?1/2)*(1/(v refh ?v refl )). e fs 1.80v < v ddad < 3.6v ? + 0.4 + 1.0 lsb 11 input leakage error 10 10 input leakage error is error due to input leakage across the r eal portion of the impedance of th e network driving the analog pi n. reducing the impedance of the network reduces this error. e il 1.80v < v ddad < 3.6v ? + 0.05 + 5lsb 12 total unadjusted error 11 e tu 1.80v < v ddad < 3.6v ? + 1.1 + 2.5 lsb
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 55 6.3.4 mcu internal clock gene ration module characteristics figure 27. icg clock basic schematic 11 total unadjusted error is the difference between the transition voltage to the current code and the ideal straight-line transfe r function. this measure of error includes inherent quantization error (1/2lsb) and circ uit error (differential, integral, zero-s cale, and full-scale) error. the specified value of e t assumes zero e il (no leakage or zero real source impedance). table 15. mcu icg dc electrical specifications (temperature range = ?40 to 85 c ambient) characteristic symbol min typ 1 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. max unit load capacitors c 1 c 2 2 2 see crystal or resonator manufacturer?s recommendation. feedback resistor low range (32k to 100 khz) high range (1m ? 16 mhz) r f 10 1 m ? mw series resistor r s 0 ? icg extal xtal crystal or resonator (see note) c 2 r f c 1 use fundamental mode crystal or ceramic resonator only. note: r s
mc13211/212/213 technical data, rev. 1.2 56 freescale semiconductor 6.3.5 mcu icg frequency specifications table 16. mcu icg frequency specifications (v dda = v dda (min) to v dda (max), temperature range = ?40 to 85 c ambient) characteristic symbol min typical max unit oscillator crystal or resonator (refs = 1) (fundamental mode crystal or ceramic resonator) low range high range , fll bypassed external (clks = 10) high range , fll engaged external (clks = 11) f lo f hi_byp f hi_eng 32 2 2 ? ? ? 100 16 10 khz mhz mhz input clock frequency (clks = 11, refs = 0) low range high range f lo f hi_eng 32 2 ? ? 100 10 khz mhz input clock frequency (clks = 10, refs = 0) f extal 0?40mhz internal reference frequency (untrimmed) f icgirclk 182.25 243 303.75 khz duty cycle of input clock 4 (refs = 0) t dc 40 ? 60 % output clock icgout frequency clks = 10, refs = 0 all other cases f icgout f extal (min) f lo (min) f extal (max) f icgdclkma x (max) mhz minimum dco clock (icgdclk) frequency f icgdclkmin 8? mhz maximum dco clock (i cgdclk) frequency f icgdclkma x ?40mhz self-clock mode (icgout) frequency 1 f self f icgdclkmin f icgdclkma x mhz self-clock mode reset (icgout) frequency f self_reset 5.5 8 10.5 mhz loss of reference frequency 2 low range high range f lor 5 50 25 500 khz loss of dco frequency 3 f lod 0.5 1.5 mhz crystal start-up time 4, 5 low range high range t cstl t csth ? ? 430 4 ? ? ms fll lock time 4, 6 low range high range t lockl t lockh ? ? 2 2 ms fll frequency unlock range n unlock ?4*n 4*n counts fll frequency lock range n lock ?2*n 2*n counts
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 57 6.4 mcu ac peripheral characteristics this section describes ac timing charac teristics for each peripheral system. 6.4.1 mcu control timing icgout period jitter, 4, 7 measured at f icgout max long term jitter (averaged over 2 ms interval) c jitter ?0.2 % f icg internal oscillator deviat ion from trimmed frequency v dd = 1.8 ? 3.6 v, (constant temperature) v dd = 3.0 v 10%, ?40 c to 85 c acc int ? ? 0.5 0.5 2 2 % 1 self-clocked mode frequency is the frequency that the dco generates when the fll is open-loop. 2 loss of reference frequency is the reference frequency detected in ternally, which transitions the icg into self-clocked mode if it is not in the desired range. 3 loss of dco frequency is the dco frequency detected internally, which transitions t he icg into fll bypassed external mode (if an external reference exists) if it is not in the desired range. 4 this parameter is characterized before qualification rather than 100% tested. 5 proper pc board layout procedures must be followed to achieve specifications. 6 this specification applies to the period of time required for the fll to lock after entering fll engaged internal or external modes. if a crystal/resonator is being used as the referenc e, this specification assumes it is already running. 7 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f icgout . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dda and v ssa and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table 17. mcu control timing parameter symbol min typical max unit bus frequency (t cyc = 1/f bus )f bus dc ? 20 mhz real-time interrupt internal oscillator period t rti 700 1300 s external reset pulse width 1 t extrst 1.5 x f self_reset ?ns reset low drive 2 t rstdrv 34 x f self_reset ?ns active background debug mode latch setup time t mssu 25 ? ns active background debug mode latch hold time t msh 25 ? ns irq pulse width 3 t ilih 1.5 x t cyc ?ns port rise and fall time (load = 50 pf) 4 slew rate control disabled slew rate control enabled t rise , t fall ? ? 3 30 ns table 16. mcu icg frequency specifications (continued) (v dda = v dda (min) to v dda (max), temperature range = ?40 to 85 c ambient) characteristic symbol min typical max unit
mc13211/212/213 technical data, rev. 1.2 58 freescale semiconductor figure 28. control reset timing figure 29. control active background debug mode latch timing figure 30. control irq timing 6.4.2 mcu timer/pwm (tpm) module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. 1 this is the shortest pulse that is guaranteed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. 2 when any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f self_reset and then samples the level on the reset pin about 38 cycles later to distingu ish external reset requests from internal requests. 3 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 85 c. table 18. tpm input timing function symbol min max unit external clock frequency f tpmext dc f bus /4 mhz external clock period t tpmext 4?t cyc external clock high time t clkh 1.5 ? t cyc external clock low time t clkl 1.5 ? t cyc input capture pulse width t icpw 1.5 ? t cyc t extrst reset pin bkgd/ms reset t mssu t msh t ilih irq
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 59 figure 31. timer external clock figure 32. timer input capture pulse t text t clkh t clkl tpmxchn t icpw tpmxchn t icpw tpmxchn
mc13211/212/213 technical data, rev. 1.2 60 freescale semiconductor 6.4.3 system spi timing table 19 describes the timing requirements for the spi system. figure 33. spi master timing (cpha = 0) table 19. spi timing no. function symbol min max unit operating frequency master f op f bus /2048 f bus /2 = 8 mhz hz 1 sck period master t sck 22048t cyc 2 enable lead time master t lead 1 / 2?t sck 3 enable lag time master t lag 1 / 2?t sck 4 clock (sck) high or low time master t wsck 62.5 1024 t cyc ns 5 data setup time (inputs) master t su 15 ? ns 6 data hold time (inputs) master t hi 0?ns 7 data valid (after sck edge) master t v ?25ns 8 data hold time (outputs) master t ho 0?ns 9rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns 10 fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns sck (output) sck (output) miso (input) mosi (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) 1 4 5 6 7 8 9 10 4 2 ss 1 (output) 3
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 61 6.4.4 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power sources other than the normal v dd supply. table 20. flash characteristics characteristic symbol min typical max unit supply voltage for program/erase v prog/erase 2.1 3.6 v supply voltage for read operation 0 < f bus < 8 mhz 0 < f bus < 20 mhz v read 1.8 2.08 3.6 3.6 v internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz internal fclk period (1/fclk) t fcyc 56.67 s byte program time (random location) (2) t prog 9t fcyc byte program time (burst mode) (2) t burst 4t fcyc page erase time 2 2 these values are hardware state machine controlled. user c ode does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc mass erase time (2) t mass 20,000 t fcyc program/erase endurance 3 t l to t h = ?40 c to + 85 c t = 25 c 3 typical endurance for flash was evaluated for this product family on t he 9s12dx64. for additional information on how freescale semiconductor defines typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory . 10,000 100,000 ? ? cycles data retention 4 4 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale semiconductor defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for non-volatile memory. t d_ret 15 100 ? years
mc13211/212/213 technical data, rev. 1.2 62 freescale semiconductor 7 application considerations the following sections describe crystal requirements and rf port options for e nd user applications. 7.1 crystal oscillator reference frequency the 802.15.4 standard requires that several frequency tolerances be kept within 40 ppm accuracy. this means that a total offset up to 80 ppm between tran smitter and receiver will s till result in acceptable performance. the mc1321x transceiver provides onboard crys tal trim capacitors to a ssist in meeting this performance. the primary determini ng factor in meeting the 802.15.4 stan dard, is the tolerance of the crystal oscillator referenc e frequency. a number of factors can cont ribute to this tolerance and a crystal specification will quantify each of them: 1. the initial (or make) tolerance of the crystal resonant frequency itself. 2. the variation of the crystal res onant frequency with temperature. 3. the variation of the crystal resonant frequency with time , also commonly known as aging. 4. the variation of the crystal re sonant frequency with load cap acitance, also commonly known as pulling. this is affected by: a) the external load capacitor values - init ial tolerance and variation with temperature. b) the internal trim capacitor values - initial tolerance and variation with temperature. c) stray capacitance on the crystal pin nodes - incl uding stray on-chip capaci tance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. whether or not a frequency trim st ep will be performed in production 7.1.1 crystal oscillator design considerations freescale requires that a 16 mhz crystal with a <9 pf load capacitance is used. the mc1321x does not contain a reference divider, so 16 mhz is the only frequency that can be used. a crysta l requiring higher load capacitance is prohibited because a higher lo ad on the amplifier circuit may compromise its performance. the crystal manuf acturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. the osci llator amplifier configuration used in the mc1321x requires two balanced load capacitors from each terminal of the crysta l to ground. as such, the capacitors are seen to be in series by the crystal, so each must be <18 pf for proper loading. in the figure 34 crystal reference schematic, the external lo ad capacitors are shown as 6.8 pf each, used in conjunction with a crystal that requires an 8 pf load capacitance. the default internal trim capacitor value (2.4 pf) and stray capacitance total value (6.8 pf) sum up to 9.2 pf giving a total of 16 pf. the value for the stray capacitance was determin ed empirically assuming the default internal trim capacitor value and for a specific board layout. a different board layout may re quire a different external load capacitor value. the on-chip trim capability may be us ed to determine the closest standard value by adjusting the trim value via the spi and observing the frequency at clko. each internal trim load capacitor has a trim range of approximately 5 pf in 20 ff steps. initial tolerance for the internal trim capacitance is approximately 15%.
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 63 since the mc1321x contains an on-chip reference frequency trim cap ability, it is possible to trim out virtually all of the initial tole rance factors and put th e frequency within 0.12 ppm on a board-by-board basis. individual trimming of each board in a production environment allows use of the lowest cost crystal, but requires that each board go through a trim ming procedure. this st ep can be avoided by using/specifying a crystal with a tighter stability tolerance, but the crysta l will be slightly higher in cost. a tolerance analysis budget may be created using all the previously stated factors. it is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using rss (root-sum-squa re) analysis. the aging factor is usually specified in pp m/year and the product designer can dete rmine how many years are to be assumed for the product lifetime. taki ng all of the factors into account, the product designer can determine the needed specifications for the crystal and ex ternal load capacitors to meet the 802.15.4 standard. figure 34. mc1321x modem crystal circuit 7.1.2 crystal requirements the suggested crystal specificat ion for the mc1321x is shown in table 21 . a number of the stated parameters are related to desired package, desired te mperature range and use of crystal capacitive load trimming. for more design details and su ggested crystals, see application note an3251, reference oscillator crystal requirements for mc1319x, mc1320x, and mc1321x . table 21. mc1321x crystal specifications 1 parameter value unit condition frequency 16.000000 mhz frequency tolerance (cut tolerance) 2 10 ppm at 25 c frequency stability (temperature drift) 3 15 ppm over desired temperature range aging 4 2 ppm max equivalent series resistance 5 43 ? max load capacitance 6 5 - 9 pf y1 16mhz c10 6.8pf c11 6.8pf y1 = daishinku kds - dsx321g zd00882 xtal 1 27 xtal 2 28 u3 mc 1321x
mc13211/212/213 technical data, rev. 1.2 64 freescale semiconductor 7.2 low power considerations ? program and use the modem io pi ns properly for low power operation ? all unused modem gpiox signals must be used one of 2 ways: ? if the off mode is to be us ed as a long term low power m ode, unused gpio should be tied to ground. the default gpio mode is an input and there will be no conflict. ? if only hibernate and/ or doze modes are used as long te rm low power modes, the gpio should programmed as outputs in the low state. ? when modem gpio are used as outputs: ? pullup resistors should be provi ded (can be provided by the mcu io pin if tied to the mcu) if the modem off condition is to be used as a long term low power mode. ? during hibernate and/or doze modes, the gp io will retain its programmed output state. ? if the modem gpio is used as an input, the gpio should be driven by its source during all low power modes or a pullup resi stor should be provided. ? digital outputs irq , miso, and clko: ? miso - is always an output. during hibern ate, doze, and active modes, the default condition is for the miso output to go to tristate when ce is de-asserted, and this can cause a problem with the mcu because one of its i nputs can float. program control_b register 07, bit 11, miso_hiz_en = 0 so that miso is driven low when ce is de-asserted. as a result, miso will not float when doze or hibernate mode is enabled. ?irq - is an open drain output (od) and shoul d always have a pullup resistor (typically provided by the mcu io). irq acts as the interrupt request output. note it is good practice to have the irq interrupt input to the mcu disabled during the hardware reset to the modem. after releasing the modem hardware reset, the interrupt request input to the mcu can then be enabled to await the irq that signifies the modem is re ady and in idle mode; this can prevent a possible extraneous false interrupt request. ? clko - is always an output. during hibernate clko retains it s output state, but does not toggle. during doze, clko may toggle de pending on whether it is being used. shunt capacitance <2 pf max mode of oscillation fundamental 1 user must be sure manufacturer specif ications apply to the desired package. 2 a wider frequency tolerance may acceptable if app lication uses trimming at production final test. 3 a wider frequency stability may be acceptable if a pplication uses trimming at production final test. 4 a wider aging tolerance may be acceptable if applic ation uses trimming at production final test. 5 higher esr may be acceptable with lower load capacitance. 6 lower load capacitance can allow higher esr and is better for low temperature operation in doze mode. table 21. mc1321x crystal specifications 1 (continued) parameter value unit condition
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 65 ? when the mcu is used in low po wer modes, be sure that all u nused io are programmed properly for low power operation (typically best case is as outputs in the low state). the mc1321x is commonly used with the freescale mc9s 08gt/gb 8-bit devices . for these mcus: ? use only stop2 and stop3 modes (not stop1) wi th these devices where the gpio states are retained. the mcu must retain control of the mc1321x io during low power operation. ? as stated above all unused gp io should be programmed as out puts low for lowest power and no floating inputs. ? the mcu has io signals that are not pinned-ou t on the package. these signals must also be initialized (even though they cannot be used) to prevent floating inputs. 7.3 rf single port appli cation with an f antenna figure 35 shows a typical single port rf application t opology in which part count is minimized and a printed copper f antenna is used fo r low cost. only the rf in port of the mc1321x is required because the differential port is bi-dir ectional and uses the on-chip t/r swit ch. matching to near 50 ohms is accomplished with l1, l2, l3, and the traces on the pcb. a balun transforms th e differential signal to single-ended to interface with the f antenna. the proper dc bias to the rfin_x (p ao_x) pins is provided through the balun. the ct_bias pin provides the proper bias voltage point to th e balun depending on operation, that is , ct_bias is at vdda voltage for transmit and is at ground for receive. ct_bias is switched between these two voltages based on the operation. capacitor c2 provides some high frequency bypass to the dc bias point. the l3/c1 network provides a simple bandpass filter to limit out-of-band harm onics from the transmitter. note passive component values can vary as a function of circuit board layout as required to obtain best ma tching and rf performance. figure 35. rf single port application with an f-antenna l2 3.9nh 5 1 6 2 3 4 z1 ldb212g4005c-001 l3 3. 9 n h c1 1.0pf r1 0r r2 0r not mount ed 1 2 5 3 4 j1 sma_edge_recepta c c2 10pf an t1 f_antenna l1 1.5nh l4 1.5nh gpio1 44 pao_m 39 pao_p 38 rfin_p 36 rfin_m 35 ct_bias 34 u1 mc1321x
mc13211/212/213 technical data, rev. 1.2 66 freescale semiconductor 7.4 rf dual port appli cation with an f-antenna figure 36 shows a typical dual port appli cation topology which also uses a printed copper f antenna. both the rfin and pao ports are used and the internal t/r switch is bypassed. matching is provided for both differential ports by l5, l6, l7, and l9 and c4 and c7. a balun is used for both receive and transmit paths which are provided by the external t/r switch, ic1. this implementa tion, while more complicated, gives better performance due to the reduced loss of the external t/r switch and the more optimum match provided to the pao and rfin ports. the switch control is connected to the ct_bias pin wh ich serves as its control signal. the ct_bias signal can be programmed to be active high or active low (depending on tx versus rx) and will switch appropriately based on the radio operation. no inte raction with the mcu on an operation-by-operation basis is required. note passive component values can vary as a function of circuit board layout as required to obtain best ma tching and rf performance. the vdd voltage to the antenna swit ch is connected to gpio1. this is a useful feature when gpio1 is programmed as an ?out of idle? status indicator. when the radio is out of idle (or active), the antenna switch is powered. in this manner, the antenna switch only consumes curr ent when it needs to be active. the gpio1 can only be used as a vdd source for a very low current load. figure 36. rf dual port application with an f-antenna 5 1 6 2 3 4 z2 ldb212g4005c-001 l5 4.7nh l6 4.7nh c6 10pf vd da vdd 6 in 5 vcont 4 out1 1 out2 3 gnd 2 ic1 pg2012tk-e2 c3 10pf c8 10pf 5 1 6 2 3 4 z3 ldb212g4005c-001 l8 2.2nh c9 1. 8pf r3 0r r4 0r not mounted 1 2 5 3 4 j2 sma_edge_receptacle_female ant2 f_antenna l7 3.3nh l9 3.3nh c5 10pf c4 1.0pf c7 1.8pf gpio1 44 pao_m 39 pao_p 38 rfin_p 36 rfin_m 35 ct_bias 34 u2 mc1321x
mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 67 8 mechanical diagrams figure 37 and figure 38 show the mc1321x mech anical information. figure 37. mc1321x mechanical (1 of 2)
mc13211/212/213 technical data, rev. 1.2 68 freescale semiconductor figure 38. mc1321x mechanical (2 of 2)
notes mc13211/212/213 technical data, rev. 1.2 freescale semiconductor 69
document number: mc1321x rev. 1.2 05/2007 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale se miconductor assume any liability arising out of the application or use of any product or circuit, and sp ecifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor d oes not convey any lice nse under its patent rights nor the rights of others. freescale semiconduc tor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other ap plications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal inju ry or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semico nductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against a ll claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005, 2006, 2007. all rights reserved.

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